LLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA...
A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: “Formal property verification...
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Formal Verification Best Practices: Investigating A Deadlock
To ensure a design is deadlock free with formal verification, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the...
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Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s...
By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera...
View ArticleMeasuring The Complexity Of Processor Bugs To Improve Testbench Quality
I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the...
View ArticleComparing And Spotting The Difference Between Two Simulations
Comparing is a basic skill we all use in our daily lives in order to understand reality and analyze situations. When it comes to chip verification, the fundamental task of checking also involves...
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Four Requirements To Improve Chip Design Debug
Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs...
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Adding Value To Open-Source RISC-V Cores With Verification
By Steve Richmond (Silicon Labs), Mike Thompson (OpenHW Group), and Lee Moore (Imperas Software) Modern SoC verification has matured to the point that some are suggesting the use of the word...
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Verification Convergence: Problem Definition
A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor...
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I’m Almost Done
The city of Belgrade is renovating the street where I live. They are also building a new building next to mine so that I can see the construction work from my balcony. Last week, they blocked the...
View ArticleConfusion Persists In Verification Terms
I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am...
View ArticleThe Future of UVM
It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use...
View ArticleThe Future of UVM
It’s time for a frank discussion on the future of [gettech id=”31055″ comment=”UVM”]. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long...
View ArticleThe Future of UVM
It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use...
View ArticleTestbench Qualification for Simulation and Formal Verification Signoff
The post Testbench Qualification for Simulation and Formal Verification Signoff appeared first on Semiconductor Engineering.
View ArticleAbstract Verification
Verification relies on a separation of concerns. Otherwise the task has no end. Sometimes we do it without thinking, but as an industry, we have never managed to fully define it such that it can become...
View ArticleAnalyzing Testbench Design Performance Using Verdi Performance Analyzer
Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of...
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Shift-Left Low Power Verification With UPF Information Model
By Himanshu Bhatt, Shreedhar Ramachandra and Narayana Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the...
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When Verification Leads
Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, CEO for VTool; Adnan Hamid, CEO for Breker Verification;...
View ArticleUtilizing More Data To Improve Chip Design
Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out...
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Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research...
As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the...
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