Confusion Persists In Verification Terms
I find it amazing that an area of technology that attempts to show, beyond a reasonable doubt, that a design will work before it is constructed can be so bad at getting some basic things right. I am...
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I’m Almost Done
The city of Belgrade is renovating the street where I live. They are also building a new building next to mine so that I can see the construction work from my balcony. Last week, they blocked the...
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Verification Convergence: Problem Definition
A while ago, I had to go to the ER with my friend who suddenly had a numb feeling in his face. He felt okay (and everything else is okay with him), but better be safe than sorry. While the doctor...
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Adding Value To Open-Source RISC-V Cores With Verification
By Steve Richmond (Silicon Labs), Mike Thompson (OpenHW Group), and Lee Moore (Imperas Software) Modern SoC verification has matured to the point that some are suggesting the use of the word...
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Four Requirements To Improve Chip Design Debug
Debug has always been a painful and unavoidable part of semiconductor design and, despite many technological advances, it remains one of the dominant tasks in chip development. At one time, most bugs...
View ArticleComparing And Spotting The Difference Between Two Simulations
Comparing is a basic skill we all use in our daily lives in order to understand reality and analyze situations. When it comes to chip verification, the fundamental task of checking also involves...
View ArticleMeasuring The Complexity Of Processor Bugs To Improve Testbench Quality
I am often asked the question “When is the processor verification done?” or in other words “how do I measure the efficiency of my testbench and how can I be confident in the quality of the...
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Extending The Benefits Of UVM To Include AMS: An Update On Accellera’s...
By Tom Fitzpatrick and Peter Grove SoC teams can be divided up into design and verification groups. For digital designs, the Universal Verification Methodology (UVM), initially developed by Accellera...
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Formal Verification Best Practices: Investigating A Deadlock
To ensure a design is deadlock free with formal verification, one approach consists in verifying that it is “always eventually” able to respond to a request. The wording is important. Regardless of the...
View ArticleLLM-Assisted Generation Of Formal Verification Testbenches: RTL to SVA...
A technical paper titled “From RTL to SVA: LLM-assisted generation of Formal Verification Testbenches” was published by researchers at Princeton University. Abstract: “Formal property verification...
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