Yikes! Why Is My SystemVerilog Testbench So Slooooow?
It turns out that SystemVerilog != Verilog. OK, we all figured that out a few years ago as we started to build verification environments using IEEE 1800 SystemVerilog. While it did add design features...
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DAC 2015: Day 3
The schedule for today revolves around eating and it is perfectly balanced between the big three. The morning starts with breakfast for the Cadence panel titled “Crossing the Great Divide: How to...
View ArticlePower Estimation: Early Warning System Or False Alarm?
Semiconductor Engineering sat down with a large panel of experts to discuss the state of power estimation and to find out if the current levels of accuracy are sufficient to being able to make informed...
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Still Time to Blow Up UVM
Blowing up UVM is something I ran on my own blog a few years ago. Considering not much has changed with respect to UVM – that it continues to dominate verification circles – I figured it’s a discussion...
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Seeing Debug for What It Is
Debug is problem solving. For many hardware developers, debug is a purpose. Finding a bug is a victory! Heck, debug can be flat out heroic. I’m sure we can all think back to colleagues that put in a...
View ArticleTurning Verification Inside Out
A new motivation for rebalancing came to me during a conversation I had a couple weeks ago at the Agile Alliance Technical Conference. I had the chance to compare my day-to-day responsibilities with...
View ArticleOptimizing Testbench Acceleration Performance
Part 3 in a series of papers that demystify the performance of SystemVerilog and UVM testbenches when using an emulator for the purpose of hardware-assisted testbench acceleration. In these three...
View ArticleThe Future of UVM
It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use...
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Portable Stimulus Status Report
The first release of the Portable Stimulus (PS) standard is slated for early next year. If it lives up to its promise, it could be the first new language and abstraction for verification in two...
View ArticleRaising SoC Development Productivity With Portable Stimulus
The semiconductor industry has achieved significant productivity increases by virtue of the development, deployment, and scalability of reusable design IP. The EDA industry has also achieved...
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Bugs That Kill
Are simulation-resistant superbugs stifling innovation? That is a question Craig Shirley, president and CEO of Oski Technology, asked a collection of semiconductor executives over dinner. Semiconductor...
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Trends In FPGA Verification Effort And Adoption: The 2018 Wilson Research...
As contributors and pioneers in the digital revolution, we are often so busy creating and innovating that we are compelled to focus on the trees, never mind the forest. But as we are all aware, the...
View ArticleUtilizing More Data To Improve Chip Design
Just about every step of the IC tool flow generates some amount of data. But certain steps generate a mind-boggling amount of data, not all of which is of equal value. The challenge is figuring out...
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When Verification Leads
Semiconductor Engineering sat down to discuss the implications of having an executable specification that drives verification with Hagai Arbel, CEO for VTool; Adnan Hamid, CEO for Breker Verification;...
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Shift-Left Low Power Verification With UPF Information Model
By Himanshu Bhatt, Shreedhar Ramachandra and Narayana Ganesan Low power testbenches today have no visibility of the UPF objects and their states during a low power simulation. This has been one of the...
View ArticleAnalyzing Testbench Design Performance Using Verdi Performance Analyzer
Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of...
View ArticleAbstract Verification
Verification relies on a separation of concerns. Otherwise the task has no end. Sometimes we do it without thinking, but as an industry, we have never managed to fully define it such that it can become...
View ArticleTestbench Qualification for Simulation and Formal Verification Signoff
The post Testbench Qualification for Simulation and Formal Verification Signoff appeared first on Semiconductor Engineering.
View ArticleThe Future of UVM
It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to use...
View ArticleThe Future of UVM
It’s time for a frank discussion on the future of [gettech id=”31055″ comment=”UVM”]. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long...
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