Performance continues to be key factor for the design of any complex system-on-chip (SoC). Moreover, complexity is increasing every day, which poses a challenge for engineers to track performance of the design, yet they are tasked to continuously increase chip performance. This paper describes the challenge to measure design performance and explains how Verdi Performance Analyzer enables run time performance analysis to help achieve desired chip performance. This paper presents an example based on HBM memory protocol, but the flow is protocol independent and applicable to all SoC designs.
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Authors: Abhishek Upadhyay R&D Engineer, Sr. II, Synopsys; Shaily Khare R&D Engineer II, Synopsys
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